Filter
Top Products
Central Processing Unit: Microprocessor Core (e500)
10007175-02 KAT4000 User’s Manual
3-5
L2SIZ: L2 SRAM Size—indicates the total available L2 SRAM size (read-only).
00 Reserved
01 256 kilobyte
10 512 kilobyte
11 1024 kilobyte
L2DO: L2 Data-Only mode (reserved in full memory-mapped SRAM mode)
0 L2 cache allocates entries for instruction fetches that miss in the L2
1 L2 cache allocates entries for processor data loads that miss in the L2
L2IO: L2 Instruction Only—causes L2 cache to allocate lines for instruction cache transactions only
(reserved in full memory-mapped SRAM mode).
0 L2 cache entries allocated for data loads that miss in the L2 and for processor L1
castouts
1 L2 cache allocates entries for instruction fetch misses
L2INTDIS: L2 read Intervention Disable (reserved for full memory-mapped SRAM mode)
0 Cache intervention enabled
1 Cache intervention disabled
L2SRAM: L2 cache/memory-mapped SRAM block assignment
L2SIZ = L2BLKSIZ (1 block):
000 Block 0 = cache
001 Block 0 = SRAM0
010-111 Reserved
L2SIZ = L2BLKSIZx2 (2 blocks):
Block 0 Block 1
000 Not used Cache
001 SRAM0 Not used
010 SRAM0 Cache
011 SRAM0 SRAM1
100-111 Reserved
L2LO: L2 cache Lock Overflow—sticky bit sets when an overlook condition is detected in L2 cache
(reserved in full memory-mapped SRAM mode).
0 Lock overflow not detected (clear L2LO in software)
1 Lock overflow condition detected
L2SLC: L2 Snoop Lock Clear—sticky bit sets when a snoop invalidated a locked data cache line
(reserved in full memory-mapped SRAM mode).
0 Snoop did not invalidate (clear L2LO in software)
1 Snoop invalidated a locked line