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10007175-02 KAT4000 User’s Manual
3-1
Section 3
Central Processing Unit
This chapter is an overview of the processor logic (optional) on the KAT4000. It includes
information on the CPU, exception handling, and the I/O parallel port pin assignments. The
KAT4000 uses a Freescale MPC8548 PowerQUICC III™ microprocessor. For more detailed
information, refer to the MPC8548E PowerQUICC III™ Integrated Host Processor Family Refer-
ence Manual. Refer to
Fig. 3-1 for a block diagram of the MPC8548. The MPC8548 is divided
into two main system blocks as outlined in the following table:
Table 3-1: MPC8548 Features
Category: MPC8548 Key Features:
Microprocessor Core
Embedded e500 Core Full 32-bit Book E architecture, integer data types of 8, 16, and 32 bits,
32-bit floating-point data type, capable of issuing and completing two
instructions per clock cycle, 7 pipeline stages, Auxiliary Processing
Units (APUs), page address translation, core registers, memory
management unit
L1 Cache 32-kilobyte data and 32-kilobyte instruction cache, 32-byte line,
eight-way set associative, parity protection
L2 Cache 512 kilobytes, eight-way set associative
CPU Core Speed 1 GHz or 1.3 GHz, with a 400 MHz or 533 MHz DDR2 bus, respectively
Peripheral Modules
Ethernet Four 10/100/1000 enhanced three-speed controllers (eTSEC), full-
/half-duplex support, for high-speed interconnect, a set of multiplexed
pins support two high-speed interface standards: 1x/4x serial RapidIO
(with message unit) and up to x4 PCI Express
Local Bus Controller (LBC) DDR2 SDRAM memory controller, General Purpose Chip Select
Machine (GPCM), and three User-Programmable Machines (UPM)
High-Speed Serial
Interfaces
PCIe, sRIO