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CPLD: Clock Synchronizer Registers
KAT4000 User’s Manual 10007175-02
7-14
Clock Synchronizer Primary Source Registers 1-3 (CPS1—CPS3)
The Clock Synchronizer Primary Source registers define the input primary source to the
three clock synchronizer devices. Default is 0x00 for register 1, 0x02 for register 2 and 0x04
for register 3.
Register 7-17: Clock Synchronizer Primary Source Registers 1-3 (CPS1-CPS3) at 0xfc40,0050, 0xfc40,0054, 0xfc40,0058,
respectively
Default register values for CPS1 are shown in the following row.
Default register values for CPS2 are shown in the following row.
Default register values for CPS3 are shown in the following row.
R: Reserved
PRI4-0: Primary Input Source Selection
76543210
reserved PRI4 PRI3 PRI2 PRI1 PRI0
00000
00010
00100
Bit: Input Source:
00000 aTCA CLK1 A
00001 aTCA CLK1 B
00010 aTCA CLK2 A
00011 aTCA CLK2 B
00100 aTCA CLK3 A
00101 aTCA CLK3 B
00110 AMC1 CLK1
00111 AMC1 CLK2
01000 AMC1 CLK3
01001 AMC2 CLK1
01010 AMC2 CLK2
01011 AMC2 CLK3
01100 AMC3 CLK1