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Central Processing Unit: Microprocessor Core (e500)
10007175-02 KAT4000 User’s Manual
3-7
R: Reserved should be cleared.
DOZE: Doze power management mode
0 Doze mode disabled
1 Doze mode enabled
NAP: Nap power management mode
0 Nap mode disabled
1 Nap mode enabled
SLP: Sleep power management mode enable
0 Sleep mode disabled
1 Sleep mode enabled
TBEN: Time Base Enable
0 Time base disabled (no counting)
1 Time base enabled
STBCLK: Select Time Base Clock—functions if the time base is enabled.
0 Time base is based on the processor clock
1 Time base is based on the TBCLK (RTC) input
EN_MAS7: Enable MAS7 update—enables updating MAS7 by tibre and tibsx.
0 MAS7 is not updated
1 MAS7 is updated
DCFA: Data Cache Flush Assist—forces data cache to ignore invalid sets on miss replacement selec-
tion.
0 DCFA is disabled
1 DCFA is enabled
NOPTI: No-op the data and instruction cache touch instructions
0 dcbt, dcbst, and icbt are enabled
1 dcbt, dcbst, and icbt are treated as no-ops
Hardware Implementation Dependent 1 Register
One of the functions of the Hardware Implementation Dependent 1 (HID1) register is to
display the state of the PLL_CFG[0:4] signals. The following register map summarizes HID1
for the MPC8548 CPU: