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Synchronization Clocks: MT9045 and MT9046 Clock
KAT4000 User’s Manual 10007175-02
10-2
All clock circuitry and the synchronization clock interface meets all hard requirements as
stated in the latest PICMG3.0 and AMC.0 specifications, as well as those in all relevant AMC
subspecifications.
• Backplane CLK1A/B and CLK2A/B inputs are Stratum Level 4E and Stratum Level 3 or 3E
sources, respectively, from the main system clock source. There are no specific Stratum
level requirements for the on-board output clocks that may be driven from these
Stratum level input clocks.
• Backplane CLK3A/B output is selectable as 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz.
• Backplane CLK3A/B is a derived REF clk and has no specific Stratum level quality
requirements.
• Backplane clock interfaces are designed to work within the specified bused M-LVDS
electrical requirements.
• AMC synchronization clocks are sourced from or drive the ATCA backplane
synchronization clock interface.
• AMC clock interfaces are designed to work within the specified point-to-point M-LVDS
electrical requirements.
• Clocks received from and transmitted to AMC sites have no specific Stratum level quality
requirements.
A configuration of this board is available with no clock interface circuitry.
MT9045 AND MT9046 CLOCK SYNCHRONIZERS
The MT9045 and MT9046 T1/E1 System Synchronizers contain a digital phase-locked loop
(DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary
rate transmission links. The devices have reference switching and frequency holdover capa-
bilities to help maintain connectivity during temporary synchronization interruptions. The
MT9045 is compliant to Stratum 3 and Stratum 4/4E specifications. The MT9046 can be
used to provide a cost-reduced clock interface, compliant to only Stratum 4/4E specifica-
tions.