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CPLD: Boot and Reset Registers
KAT4000 User’s Manual 10007175-02
7-10
CSR1: Clock Synchronizer 1 Reset
1 Reset
0No reset (default)
CSR2: Clock Synchronizer 2 Reset
1 Reset
0No reset (default)
CSR3: Clock Synchronizer 3 Reset
1 Reset
0No reset (default)
PCIE: PCI Express Reset
1 Reset
0No reset (default)
I2C: I
2
C Bus Reset
1 Reset
0No reset (default)
FSHR: NOR Flash Reset
1 Resets NOR flash to a known state
0No reset (default)
CER: Core Ethernet Reset
1 Reset
0No reset (default)
Reset Command Register 2 (RCR2)
Set only one bit in this register at a time. If reset when in a locked state, a clock synchronizer
will issue a loss of lock interrupt. To prevent this, mask the interrupt from registers 0xa8,
0xaC or 0xb0. The hardware will issue resets to the clock synchronizers for 10ms. Software
must wait at least 10ms before accessing these devices. Default register values are shown
in the bottom row of the register table.
Register 7-14: Reset Command Register 2 (RCR2) at 0xfc40,0028
FPR: Fat Pipe Module Reset
1 Reset
0No reset (default)
76543210
FPR DER BCR NFR reserved
0000