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Central Processing Unit: Peripheral Interface
KAT4000 User’s Manual 10007175-02
3-10
EE: External interrupt Enable—allows the processor to take external input, fixed-interval timer,
system management, performance monitor, or decrementer interrupts.
0 Disabled
1Enabled
PR: Privilege level
0 Supervisor-level instructions are executed
1 User-level instructions are executed
ME: Machine check Enable
0 Machine check interrupts disabled
1 Machine check interrupts enabled
UBLE: User BTB Lock Enable
0 Execution of the BTB lock instructions for user mode disabled
1 Execution of the BTB lock instructions for user mode enabled
IS: Instruction address Space
0 CPU directs all instruction fetches to address space 0
1 CPU directs all instruction fetches to address space 1
DS: Data address Space
0 CPU directs data memory accesses to address space 0
1 CPU directs data memory accesses to address space 1
PM: Marks a process for the Performance Monitor
0 Process is not marked
1 Process is marked
PERIPHERAL INTERFACE
The MPC8548 uses the peripheral bus to communicate with its peripherals. Ta bl e 3- 3 lists
the order in which the processor handles requests from peripherals.
Table 3-3: MPC8548 Peripheral Request Priority
Priority: Function: Request:
Highest 1 Reset in the Communication Processor Command register (CPCR)
or System Reset (SRESET*)
2 SDMA bus error
3 Commands issued to the CPCR
4 Emergency (from FCCs, MCCs, and SCCs)
5 IDMA(1-4) emulation (default option 1)
11
6FCC1 receive
7FCC1 transmit