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Central Processing Unit:
KAT4000 User’s Manual 10007175-02
3-2
Figure 3-1: MPC8548 Block Diagram
The MPC8548 PowerQUICC III version follows the PowerQUICC II communications proces-
sor. Some new MPC8548 features used on the KAT4000 include:
• e500 core 32-bit implementation of the Book E architecture
• Serial Management Channel (SMC) UART functionality implemented in SCC
• Four integrated 10/100/1000 Ethernet controllers
• Double Data Rate Two (DDR2) SDRAM memory controller
• 4-port On-Chip Network (OCeaN) full crossbar switch fabric
• Enhanced debug features
For more detailed information, reference the Freescale application note Migrating from
PowerQUICC II to PowerQUICC III.
MII, GMII,
TBI, RTBI,
RGMII, RMII
IRQs
DDR2 SDRAM
Flash GPIO
Serial
I2C
I2C
4x RapidIO
8x PCI Express
PCI-X
133 MHz
MII, GMII,
TBI, RTBI,
RGMII, RMII
MII, GMII,
TBI, RTBI,
RGMII, RMII
RTBI, RGMII,
RMII