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CPLD: Clock Synchronizer Registers
10007175-02 KAT4000 User’s Manual
7-15
Clock Synchronizer Secondary Source Registers 1-3 (CSS1—CSS3)
The Clock Synchronizer Secondary Source registers define the input secondary source to
the three clock synchronizer devices. Default is 0x01 for register 1, 0x03 for register 2 and
0x05 for register 3.
Register 7-18: Clock Synchronizer Secondary Source Registers 1-3 (CSS1-CSS3) at 0xfc40,0060, 0xfc40,0064, 0xfc40,0068,
respectively
Default register values for CSS1 are shown in the following row.
Default register values for CSS2 are shown in the following row.
Default register values for CSS3 are shown in the following row.
R: Reserved
SEC4-0: Secondary Input Source Selection
01101 AMC3 CLK2
01110 AMC3 CLK3
01111 AMC4 CLK1
10000 AMC4 CLK2
10001 AMC4 CLK3
10010 reserved
...
11111 reserved
76543210
reserved SEC4 SEC3 SEC2 SEC1 SEC0
00001
00011
00101
Bit: Input Source:
00000 aTCA CLK1 A
00001 aTCA CLK1 B
00010 aTCA CLK2 A
Bit: Input Source: