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Contents (continued)
KAT4000 User’s Manual 10007175-02
iv
10 GbE-1 GbE Fat Pipe Switch Module
PLD . . . . . . . . . . . . . . . . . . . . . . . . . . .5-16
Product ID/Version Register. .5-16
Scratch Register . . . . . . . . . . . .5-17
I2C Register . . . . . . . . . . . . . . . .5-17
Reserved Register 1 . . . . . . . . .5-18
Switch Reset Register . . . . . . .5-18
Module Status Register. . . . . .5-19
Switch GPIO Register. . . . . . . .5-19
GPIN/LED Register . . . . . . . . . .5-20
10 GbE-10 GbE Fat Pipe Switch Module5-21
sRIO Fat Pipe Switch Module . . . . . . . . 5-22
6 Memory Configuration
Boot Memory Configuration . . . . . . . . . .6-1
User Flash. . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
On-Card SDRAM . . . . . . . . . . . . . . . . . . . . .6-2
NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . .6-2
NVRAM Allocation . . . . . . . . . . . . . . . . . . .6-3
7CPLD
PLD Register Summary . . . . . . . . . . . . . . .7-1
Version and ID Registers . . . . . . . . . . . . . .7-2
Product ID Register (PIDR) . . . . . . . . 7-2
Hardware Version Register (HVR). . 7-3
PLD Version Register (PVR) . . . . . . . 7-3
Configuration Registers . . . . . . . . . . . . . .7-4
Hardware Configuration Register 0
(HCR0) . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
PLL Configuration Register (PLLC). . 7-4
Miscellaneous Registers . . . . . . . . . . . . . .7-5
LED Control Register (LEDR). . . . . . . 7-5
Jumper Settings Register (JSR). . . . . 7-6
RTM GPIO State Register (RGSR). . . 7-6
RTM GPIO Control Register (RGCR) 7-7
MISC Control Register (MISC) . . . . . 7-7
Scratch Register 1 (SCR1). . . . . . . . . 7-8
Boot and Reset Registers . . . . . . . . . . . . .7-8
Reset Event Register (RER) . . . . . . . . 7-8
Reset Command Register 1 (RCR1) 7-9
Reset Command Register 2 (RCR2)7-10
Boot Device Redirection Register
(BDRR) . . . . . . . . . . . . . . . . . . . . . . . .7-11
Clock Synchronizer Registers . . . . . . . . 7-13
Clock Synchronizer Control Registers 1-
3 (CSC1—CSC3). . . . . . . . . . . . . . . . .7-13
Clock Synchronizer Primary Source
Registers 1-3 (CPS1—CPS3) . . . . . . 7-14
Clock Synchronizer Secondary Source
Registers 1-3 (CSS1—CSS3) . . . . . . 7-15
Clock Control Registers (CCR1—CCR14)
7-17
Clock Synchronizer Interrupt Registers
(CSI1-CSI3) . . . . . . . . . . . . . . . . . . . . 7-18
JTAG Interface. . . . . . . . . . . . . . . . . . . . . 7-19
8AMC Sites
AMC Connectors . . . . . . . . . . . . . . . . . . . .8-2
AMC Signals. . . . . . . . . . . . . . . . . . . . . . . . .8-2
Pin Assignments. . . . . . . . . . . . . . . . . . . . .8-4
SATA Lines . . . . . . . . . . . . . . . . . . . . . . . . . .8-6
9 System Management
IPMC Overview . . . . . . . . . . . . . . . . . . . . . .9-1
IPMI Messaging. . . . . . . . . . . . . . . . . . . . . .9-3
IPMI Completion Codes . . . . . . . . . . 9-4
IPMB Protocol . . . . . . . . . . . . . . . . . . . . . . .9-5
SIPL Protocol . . . . . . . . . . . . . . . . . . . . . . . .9-6
Message Bridging. . . . . . . . . . . . . . . . . . . .9-7
Standard Commands. . . . . . . . . . . . . . . . .9-9
Vendor Commands . . . . . . . . . . . . . . . . 9-12
Get Status Command . . . . . . . . . . . 9-12
Get Serial Interface Properties
Command. . . . . . . . . . . . . . . . . . . . . 9-14
Set Serial Interface Properties
Command. . . . . . . . . . . . . . . . . . . . . 9-15
Get Debug Level Command . . . . . 9-16
Set Debug Level Command . . . . . . 9-17
Get Hardware Address Command 9-17
Set Hardware Address Command 9-18
Get Handle Switch Command. . . . 9-18
Set Handle Switch Command . . . . 9-19
Get Payload Communication Time-Out
Command. . . . . . . . . . . . . . . . . . . . . 9-19
Set Payload Communication Time-Out
Command. . . . . . . . . . . . . . . . . . . . . 9-20
Enable Payload Control Command9-20
Disable Payload Control Command. . .
9-20
Reset IPMC Command . . . . . . . . . . 9-21
Hang IPMC Command . . . . . . . . . . 9-21
Bused Resource Control Command. . .
9-22