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CPLD: Version and ID Registers
KAT4000 User’s Manual 10007175-02
7-2
VERSION AND ID REGISTERS
Product ID Register (PIDR)
The read-only Product ID register indicates the product name and configuration. The values
of these bits are defined by strapping resistors. Default register values are shown in the bot-
tom row of the register table.
Register 7-1: Product ID Register (PIDR) at 0xfc40,0000
0x60 CSS1 Clock Synchronizer Secondary Source 1
7-180x64 CSS2 Clock Synchronizer Secondary Source 2
0x68 CSS3 Clock Synchronizer Secondary Source 3
0x6C — Reserved —
0x70 CCR1 Clock Control, AMC1 CLK1
7-19
0x74 CCR2 Clock Control, AMC1 CLK2
0x78 CCR3 Clock Control, AMC1 CLK3
0x7C CCR4 Clock Control, AMC2 CLK1
0x80 CCR5 Clock Control, AMC2 CLK2
0x84 CCR6 Clock Control, AMC2 CLK3
0x88 CCR7 Clock Control, AMC3 CLK1
0x8C CCR8 Clock Control, AMC3 CLK2
0x90 CCR9 Clock Control, AMC3 CLK3
0x94 CCR10 Clock Control, AMC4 CLK1
0x98 CCR11 Clock Control, AMC4 CLK2
0x9C CCR12 Clock Control, AMC4 CLK3
0xA0 CCR13 Clock Control, aTCA CLK3 A
0xA4 CCR14 Clock Control, aTCA CLK3 B
0xA8 CSI1 Clock Synchronizer Interrupt 1
7-200xAC CSI2 Clock Synchronizer Interrupt 2
0xB0 CSI3 Clock Synchronizer Interrupt 3
76543210
PID1 PID0 reserved ECS PCIE
00
configuration
dependent
Address
Offset (hex): Mnemonic: Register Name:
Register Map:
(continued)