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CPLD: Configuration Registers
KAT4000 User’s Manual 10007175-02
7-4
CONFIGURATION REGISTERS
Hardware Configuration Register 0 (HCR0)
The read-only Hardware Configuration 0 register indicates various settings of the particular
product configuration. The values of these bits are defined by strapping resistors. Default
register values are configuration dependent.
Register 7-4: Hardware Configuration Register 0 (HCR0) at 0xfc40,0010
R: Reserved
BDR: BDR Enable
1 Enable boot redirect circuitry
0 Disable boot redirect circuitry
CF1, CF0, DDRF: CCB and Core Frequencies (MHz)
PLL Configuration Register (PLLC)
The PLL Configuration register indicates PLL settings for the MPC8548 processor. The initial
values of these bits are defined by strapping resistors. The values can be overwritten by
software. Default register values are configuration dependent.
Register 7-5: PLL Configuration Register (PLLC) at 0xfc40,000c
R: Reserved
76543210
reserved BDR reserved CF1 CF0 DDRF
Bits 2:0: CCB: Core:
000 400 800
001 533 800
010 400 1000
011 533 800
100 400 1200
101 533 1333
110 reserved
111 reserved
76 5 43210
R
CORE2 CORE1 CORE0
SYS3 SYS2 SYS1 SYS0