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Epson Research and Development
Page 101
Vancouver Design Center
Hardware Functional Specification S1D13505
Issue Date: 01/02/02 X23A-A-001-14
8.2.3 Panel/Monitor Configuration Registers
bit 7 EL Panel Mode Enable
When this bit = 1, EL Panel support mode is enabled. Every 262143 frames (approximately 1 hour
at 60Hz frame rate) the identical panel data is sent to two consecutive frames, i.e. the frame rate
modulation circuitry is frozen for one frame.
bits 5-4 Panel Data Width Bits [1:0]
These bits select the LCD interface data width as shown in the following table.
bit 3 Panel Data Format Select
When this bit = 1, color passive LCD panel data format 2 is selected.
When this bit = 0, passive LCD panel data format 1 is selected.
bit 2 Color/Mono Panel Select
When this bit = 1, color passive LCD panel is selected.
When this bit = 0, monochrome passive LCD panel is selected.
bit 1 Dual/Single Panel Select
When this bit = 1, dual passive LCD panel is selected.
When this bit = 0, single passive LCD panel is selected.
bit 0 TFT/Passive LCD Panel Select
When this bit = 1, TFT/D-TFD panel is selected.
When this bit = 0, passive LCD panel is selected.
bits 5-0 MOD Rate Bits [5:0]
When the DRDY pin is configured as MOD, this register controls the toggle rate of the MOD out-
put. When this register is zero, the MOD output signal toggles every FPFRAME. When this register
is non-zero, its value represents the number of FPLINE pulses between toggles of the MOD output
signal.
Panel Type Register
REG[02h] RW
EL Panel
Enable
n/a
Panel Data
Width Bit 1
Panel Data
Width Bit 0
Panel Data
Format Select
Color/Mono.
Panel Select
Dual/Single
Panel Select
TFT/ Passive
LCD Panel
Select
Table 8-3: Panel Data Width Selection
Panel Data Width Bits [1:0]
Passive LCD Panel Data
Width Size
TFT/D-TFD Panel Data Width
Size
00 4-bit 9-bit
01 8-bit 12-bit
10 16-bit 16-bit
11 Reserved Reserved
MOD Rate Register
REG[03h] RW
n/a n/a
MOD Rate Bit
5
MOD Rate Bit
4
MOD Rate Bit
3
MOD Rate Bit
2
MOD Rate Bit
1
MOD Rate Bit
0