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Epson Research and Development
Vancouver Design Center
S1D13505 13505CFG Configuration Program
X23A-B-001-04 Issue Date: 01/03/29
CRT PCLK These settings select the signal source and input clock
divisor for the CRT pixel clock (CRT PCLK).
Source The CRT PCLK source is CLKI.
Divide Specifies the divide ratio of CLKI to derive the CRT
PCLK.
Selecting “Auto” for the divisor allows the configu-
ration program to calculate the best clock divisor.
Unless a very specific clocking is required, it is best to
leave this setting on “Auto”.
Timing This field shows the actual CRT PCLK frequency used
by the configuration process calculations.
MCLK These settings select the signal source and input clock
divisor for the memory clock (MCLK).
Source The MCLK source is CLKI.
Divide Specifies the divide ratio of CLKI to derive MCLK.
Leave this setting at 1:1 ratio unless MCLK is greater
than 40MHz.
Timing This field shows the actual MCLK frequency used by
the configuration process calculations.