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Epson Research and Development
Page 97
Vancouver Design Center
Programming Notes and Examples S1D13505
Issue Date: 01/02/05 X23A-G-003-07
50, /* Memory speed in ns */
84, /* Ras to Cas Delay in ns */
30, /* Ras Access Charge time in ns */
50, /* RAS Access Charge time in ns */
16 /* Host CPU bus width in bits */
};
The following header file defines the S1D13505 HAL registers.
/*===========================================================================
** HAL_REGS.H
** Created 1998, Epson Research & Development
** Vancouver Design Center.
** Copyright(c) Epson Research and Development Inc. 1997, 1998. All rights
reserved.
=============================================================================*/
#ifndef __HAL_REGS_H__
#define __HAL_REGS_H__
/*
** 1355 register names
*/
#define REG_REVISION_CODE 0x00
#define REG_MEMORY_CONFIG 0x01
#define REG_PANEL_TYPE 0x02
#define REG_MOD_RATE 0x03
#define REG_HORZ_DISP_WIDTH 0x04
#define REG_HORZ_NONDISP_PERIOD 0x05
#define REG_HRTC_START_POSITION 0x06
#define REG_HRTC_PULSE_WIDTH 0x07
#define REG_VERT_DISP_HEIGHT0 0x08
#define REG_VERT_DISP_HEIGHT1 0x09
#define REG_VERT_NONDISP_PERIOD 0x0A
#define REG_VRTC_START_POSITION 0x0B
#define REG_VRTC_PULSE_WIDTH 0x0C
#define REG_DISPLAY_MODE 0x0D
#define REG_SCRN1_LINE_COMPARE0 0x0E
#define REG_SCRN1_LINE_COMPARE1 0x0F
#define REG_SCRN1_DISP_START_ADDR0 0x10
#define REG_SCRN1_DISP_START_ADDR1 0x11
#define REG_SCRN1_DISP_START_ADDR2 0x12
#define REG_SCRN2_DISP_START_ADDR0 0x13
#define REG_SCRN2_DISP_START_ADDR1 0x14
#define REG_SCRN2_DISP_START_ADDR2 0x15
#define REG_MEM_ADDR_OFFSET0 0x16
#define REG_MEM_ADDR_OFFSET1 0x17
#define REG_PIXEL_PANNING 0x18