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Epson Research and Development
Vancouver Design Center
S1D13505 Hardware Functional Specification
X23A-A-001-14 Issue Date: 01/02/02
.
Figure 3-7: Typical System Diagram (Philips PR31500/PR31700 Bus)
.
Figure 3-8: Typical System Diagram (Toshiba TX3912 Bus)
S1D13505F00A
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLKI
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0]
4/8/16-bit
LCD
Display
LCDPWR
WE#
A[11:0]
D[15:0]
RAS#
1Mx16
LCAS#
UCAS#
MA[11:0]
MD[15:0]
WE#
RAS#
LCAS#
UCAS#
FPM/EDO-DRAM
Power
Management
SUSPEND#
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
IREF
IREF
PR31500
BUS
RESET#
/WE
D[31:16]
/CARDxCSL
/RD
/CARDxWAIT
A[12:0]
DCLKOUT
WE0#
RD/WR#
AB[12:0]
DB[15:0]
WE1#
BS#
RD#
M/R#
CS#
BUSCLK
WAIT#
RESET#
/CARDxCSH
AB[16:13]
ALE
/CARDREG
/CARDIORD
AB20
AB19
AB18
AB17
/CARDIOWR
/PR31700
Philips
S1D13505F00A
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLKI
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0]
4/8/16-bit
LCD
Display
LCDPWR
WE#
A[11:0]
D[15:0]
RAS#
1Mx16
LCAS#
UCAS#
MA[11:0]
MD[15:0]
WE#
RAS#
LCAS#
UCAS#
FPM/EDO-DRAM
Power
Management
SUSPEND#
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
IREF
IREF
BUS
RESET#
WE*
D[23:16]
CARDxCSL*
RD*
CARDxWAIT*
A[12:0]
DCLKOUT
WE0#
RD/WR#
AB[12:0]
DB[15:8]
WE1#
BS#
RD#
M/R#
CS#
BUSCLK
WAIT#
RESET#
CARDxCSH*
AB[16:13]
ALE
CARDREG*
CARDIORD*
AB20
AB19
AB18
AB17
CARDIOWR*
Toshiba
TX3912
DB[7:0]
D[31:24]