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Epson Research and Development
Page 41
Vancouver Design Center
Programming Notes and Examples S1D13505
Issue Date: 01/02/05 X23A-G-003-07
6.2.1 Registers
The Software Suspend Mode Enable bit initiates Software suspend when set to 1. Setting
the bit back to 0 returns the controller back to normal mode.
The Suspend Refresh Select Bits specify the type of DRAM refresh used during suspend
mode. The type of DRAM refresh is as follows:
Note
The Suspend Refresh Select bits should never be changed while in suspend mode.
The Power Save Status bit is a read-only status bit which indicates the power-save state of
the S1D13505. When this bit returns a 1, the panel is powered-off and the memory is in a
suspend memory refresh mode. When this bit returns a 0, the S1D13505 is either powered-
on, in transition of powering-on, or in transition of powering-off.
REG[1Ah] Power Save Configuration Register
Power Save
Status (RO)
n/a n/a n/a
LCD Power
Disable
Suspend
Refresh
Select Bit 1
Suspend
Refresh
Select Bit 0
Software
Suspend
Mode Enable
REG[1Ah] Power Save Configuration Register
Power Save
Status (RO)
n/a n/a n/a
LCD Power
Disable
Suspend
Refresh
Select Bit 1
Suspend
Refresh
Select Bit 0
Software
Suspend
Mode Enable
Table 6-1: Suspend Refresh Selection
Suspend Refresh Select Bits [1:0] DRAM Refresh Type
00 CAS-before-RAS (CBR) refresh
01 Self-Refresh
1X No Refresh
REG[1Ah] Power Save Configuration Register
Power Save
Status (RO)
n/a n/a n/a
LCD Power
Disable
Suspend
Refresh
Select Bit 1
Suspend
Refresh
Select Bit 0
Software
Suspend
Mode Enable