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Epson Research and Development
Page 13
Vancouver Design Center
13505CFG Configuration Program S1D13505
Issue Date: 01/03/29 X23A-B-001-04
The S1D13505 may use as many as three input clocks or as few as one. The more clocks
used the greater the flexibility of choice in display type and memory speed.
CLKI This setting determines the frequency of CLKI. CLKI is
the source clock for all of the S1D13505 internal clocks.
Select “LCD Auto” or “CRT Auto” to have the CLKI
frequency determined automatically based on settings
made on the Panels or CRT configuration tabs. After
completing the other configurations, the required CLKI
frequency will be displayed in blue in the Auto section.
If the CLKI frequency must be fixed to a particular rate,
set this value by selecting a preset frequency from the
drop down list or entering the desired frequency in
MHz.
BUSCLK This setting determines the frequency of the bus
interface clock (BUSCLK).
The BUSCLK frequency must be specified. Set this
value by selecting a preset frequency from the drop
down list or entering the desired frequency in MHz.
LCD PCLK These settings select the signal source and input clock
divisor for the panel pixel clock (LCD PCLK).
Source The LCD PCLK source is MCLK.
Divide Specifies the divide ratio of MCLK to derive the LCD
PCLK.
Selecting “Auto” for the divisor allows the configu-
ration program to calculate the best clock divisor.
Unless a very specific clocking is being specified, it is
best to leave this setting on “Auto”.
Timing This field shows the actual LCD PCLK frequency used
by the configuration process calculations.