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Epson Research and Development
Vancouver Design Center
S1D13505 Programming Notes and Examples
X23A-G-003-07 Issue Date: 01/02/05
Delay Too Long
To shorten 128 frame delay on LCDPWR.
1. Set REG[23h] bit 7 to 1 - Blanks screen by disabling the FIFO.
2. Set REG[04h] to 3 (changes display width to 32 pixels)
Set REG[08h] to 0 (changes display height to 1 line)
- This changes the display resolution to minimum (32x1).
3. Set REG[1Ah] bit 0 to 0 - Enables power save mode.
4. Wait delay time (based on new frame rate, see
S1D13505 Hardware Functional Spec-
ification
, document number X23A-A-001-xx)
- at this time any clocks can be disabled.
.
.
.
5. Enable any clocks that were disabled in step 4.
6. Set REG[1Ah] bit 0 to 0 - Disables power save mode.
7. Set REG[04h] to original setting
Set REG[08h] to original setting
- Re-initializes the original resolution.
8. Set REG[023h] bit 7 to 0 - Un-blanks screen by enabling the FIFO.
6.2 Software Power Save
The S1D13505 supports a software initiated suspend power save mode. This mode is
controllable using the Software Suspend Mode Enable bit in REG[1Ah]. The type of
memory refresh used during suspend can also be controlled by software.
While software suspend is enabled the following conditions apply.
• display(s) are inactive
• registers are accessible
• memory is not-accessible
• LUT is accessible