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Epson Research and Development
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Programming Notes and Examples S1D13505
Issue Date: 01/02/05 X23A-G-003-07
2.1 Miscellaneous
This section of the notes contains recommendations which can be set at initialization time
to improve display image quality.
At high color depths the display FIFO introduces two conditions which must be accounted
for in software. Simultaneous display while using a dual passive panel introduces another
possible register change.
Display FIFO Threshold
At 15/16 bit-per-pixel the display FIFO threshold (bits 0-4 of register [23h]) must be
programmed to a value other than '0'. Product testing has shown that at these color depths
a better quality image results when the display FIFO threshold is set to a value of 1Bh.
Memory Address Offset
When an 800x600 display mode is selected at 15 or 16 bpp, memory page breaks can
disrupt the display buffer fetches. This disruption produces a visible flicker on the display.
To avoid this set the Memory Address Offset (Reg [16h] and Reg [17h]) to 200h. This sets
a 1024 pixel line which aligns the memory page breaks and reduces any flicker.
Half Frame Buffer Disable
The half frame buffer stores the display data for dual drive LCD panels. During LCD only
or simultaneous display using a single LCD panel, no special adjustments are required.
However, for simultaneous display using a dual drive LCD panel, the half frame buffer
must be disabled (REG[1Bh] bit 0 = 1). This results in reduced contrast on the LCD panel
because the duty cycle of the LCD is halved. To compensate for this change, the pattern
used by the Frame Rate Modulator (FRM) may need to be adjusted. Programming the
Alternate FRM Register (REG[31h]) with the recommended value of FFh may produce
more visually appealing output.
For further information on the half frame buffer and the Alternate FRM Register see the
S1D13505 Hardware Functional Specification
, document number X23A-A-001-xx.