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S1D13505F00A Register Summary X23A-R-001-04
Page 2 01/02/06
3 DRAM Refresh Rate Select
4 Panel Data Width Selection
5 Simultaneous Display Option Selection
6 Number of Bits-Per-Pixel Selection
7 PCLK Divide Selection
8 Suspend Refresh Selection
9 Minimum Memory Timing Selection
10 RAS#-to-CAS# Delay Timing Select
11 RAS Precharge Timing Select
12 Ink/Cursor Start Address Encoding
DRAM Refresh
Rate Select Bits
[2:0]
CLKI Frequency
Divisor
Example Refresh
Rate for CLKI =
33MHz
Example period for
256 refresh cycles at
CLKI = 33MHz
000 64 520 kHz 0.5 ms
001 128 260 kHz 1 ms
010 256 130 kHz 2 ms
011 512 65 kHz 4 ms
100 1024 33 kHz 8 ms
101 2048 16 kHz 16 ms
110 4096 8 kHz 32 ms
111 8192 4 kHz 64 ms
Panel Data Width Bits
[1:0]
Passive LCD Panel Data Width
Size
TFT Panel Data Width Size
00 4-bit 9-bit
01 8-bit 12-bit
10 16-bit 16-bit
11 Reserved Reserved
Simultaneous Display Option Select Bits
[1:0]
Simultaneous Display Mode
00 Normal
01 Line Doubling
10 Interlace
11 Even Scan Only
Bit-Per-Pixel Select Bits [2:0] Color Depth (Bit-Per-Pixel)
000 1 bpp
001 2 bpp
010 4 bpp
011 8 bpp
100 15 bpp
101 16 bpp
110-111 Reserved
PCLK Divide Select Bits [1:0] MCLK: PCLK Frequency Ratio
00 1: 1
01 2: 1
10 3: 1
11 4: 1
Suspend Refresh Select Bits [1:0] DRAM Refresh Type
00 CAS-before-RAS (CBR) Refresh
01 Self-Refresh
1x No Refresh
REG[22h] Bits [6:5] N
RC
Minimum Random Cycle
Width (t
RC
)
00 5 5
01 4 4
10 3 3
11 Reserved Reserved
REG[22h] Bit 4 N
RCD
RAS#-to-CAS# Delay (t
RCD
)
02 2
11 1
REG[22h] Bits [3:2] N
RP
RAS Precharge Width (t
RP
)
00 2 2
01 1.5 1.5
10 1 1
11 Reserved Reserved
Ink/Cursor Start Address Bits [7:0] Start Address (Bytes)
0 Display Buffer Size – 1024
n = 255...1 Display Buffer Size – (n x 8192)