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Epson Research and Development
Vancouver Design Center
S1D13505 Programming Notes and Examples
X23A-G-003-07 Issue Date: 01/02/05
/*
** Step 4: Set Performance Enhancement 0 register
*/
*(pRegs + 0x22) = 0x24; /* 0010 0100 */
/*
** Step 5: Set the rest of the registers in order.
*/
/*
** Register 2: Panel Type - 16-bit, format 1, color, dual, passive.
*/
*(pRegs + 0x02) = 0x26; /* 0010 0110 */
/*
** Register 3: Mod Rate
*/
*(pRegs + 0x03) = 0x00; /* 0000 0000 */
/*
** Register 4: Horizontal Display Width (HDP) - 640 pixels
** (640 / 8) - 1 = 79t = 4Fh
*/
*(pRegs + 0x04) = 0x4f; /* 0100 1111 */
/*
** Register 5: Horizontal Non-Display Period (HNDP)
** PCLK
** Frame Rate = -----------------------------
** (HDP + HNDP) * (VDP + VNDP)
**
** 16,500,000
** = -----------------------------
** (640 + HNDP) * (480 + VNDP)
**
** HNDP and VNDP must be calculated such that the desired frame rate
** is achieved.
*/
*(pRegs + 0x05) = 0x1F; /* 0001 1111 */
/*
** Register 6: HRTC/FPLINE Start Position - applicable to CRT/TFT only.
*/
*(pRegs + 0x06) = 0x00; /* 0000 0000 */
/*
** Register 7: HRTC/FPLINE Pulse Width - applicable to CRT/TFT only.
*/
*(pRegs + 0x07) = 0x00; /* 0000 0000 */
/*
** Registers 8-9: Vertical Display Height (VDP) - 480 lines.
** 480/2 - 1 = 239t = 0xEF
*/
*(pRegs + 0x08) = 0xEF; /* 1110 1111 */
*(pRegs + 0x09) = 0x00; /* 0000 0000 */
/*