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Epson Research and Development
Page 91
Vancouver Design Center
Programming Notes and Examples S1D13505
Issue Date: 01/02/05 X23A-G-003-07
** Register A: Vertical Non-Display Period (VNDP)
** This register must be programed with register 5 (HNDP)
** to arrive at the frame rate closest to the desired
** frame rate.
*/
*(pRegs + 0x0A) = 0x01; /* 0000 0001 */
/*
** Register B: VRTC/FPFRAME Start Position - applicable to CRT/TFT only.
*/
*(pRegs + 0x0B) = 0x00; /* 0000 0000 */
/*
** Register C: VRTC/FPFRAME Pulse Width - applicable to CRT/TFT only.
*/
*(pRegs + 0x0C) = 0x00; /* 0000 0000 */
/*
** Register D: Display Mode - 8 BPP, LCD disabled.
*/
*(pRegs + 0x0D) = 0x0C; /* 0000 1100 */
/*
** Registers E-F: Screen 1 Line Compare - unless setting up for
** split screen operation use 0x3FF.
*/
*(pRegs + 0x0E) = 0xFF; /* 1111 1111 */
*(pRegs + 0x0F) = 0x03; /* 0000 0011 */
/*
** Registers 10-12: Screen 1 Display Start Address - start at the
** first byte in display memory.
*/
*(pRegs + 0x10) = 0x00; /* 0000 0000 */
*(pRegs + 0x11) = 0x00; /* 0000 0000 */
*(pRegs + 0x12) = 0x00; /* 0000 0000 */
/*
** Register 13-15: Screen 2 Display Start Address - not applicable
** unless setting up for split screen operation.
*/
*(pRegs + 0x13) = 0x00; /* 0000 0000 */
*(pRegs + 0x14) = 0x00; /* 0000 0000 */
*(pRegs + 0x15) = 0x00; /* 0000 0000 */
/*
** Register 16-17: Memory Address Offset - this address represents the
** starting WORD. At 8BPP our 640 pixel width is 320
** WORDS
*/
*(pRegs + 0x16) = 0x40; /* 0100 0000 */
*(pRegs + 0x17) = 0x01; /* 0000 0001 */
/*
** Register 18: Pixel Panning
*/
*(pRegs + 0x18) = 0x00; /* 0000 0000 */