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Epson Research and Development
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Vancouver Design Center
S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual S1D13505
Issue Date: 01/02/05 X23A-G-004-05
1 Introduction
This manual describes the setup and operation of the S5U13505B00C Rev. 1.0 Evaluation Board.
Implemented using the S1D13505 Embedded RAMDAC LCD/CRT Controller, the
S5U13505B00C is designed for the ISA bus environment. It also provides CPU/Bus interface
connectors for non-ISA bus support.
For more information regarding the S1D13505, refer to the S1D13505 Hardware Functional Speci-
fication, document number X23A-A-001-xx.
1.1 Features
• 128-pin QFP15 surface mount package.
• SMT technology for all appropriate devices.
• 4/8-bit monochrome passive LCD panel support.
• 4/8/16-bit color passive LCD panel support.
• 9/12/18-bit LCD TFT/D-TFD panel support.
• Embedded RAMDAC for CRT support.
• 16-bit ISA bus support.
• Oscillator support for CLKI (up to 40.0MHz).
• 5.0V 1M x 16 EDO-DRAM (2M byte).
• Support for software and hardware suspend modes.
• On-board adjustable LCD bias power supply (+24..38V or -24..14V).
• CPU/Bus interface header strips for non-ISA bus support.