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Epson Research and Development
Page 79
Vancouver Design Center
Hardware Functional Specification S1D13505
Issue Date: 01/02/02 X23A-A-001-14
Figure 7-27: 8-Bit Single Monochrome Passive LCD Panel A.C. Timing
1. Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
2. t1
min
= t4
min
- 14Ts
3. t4
min
= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts
4. t5
min
= [(((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8)-1] Ts
5. t6
min
= [((REG[05h] bits [4:0]) + 1)*8 - 25] Ts
6. t9
min
= [((REG[05h] bits [4:0]) + 1)*8 - 16] Ts
Table 7-24: 8-Bit Single Monochrome Passive LCD Panel A.C. Timing
Symbol Parameter Min Typ Max Units
t1
FPFRAME setup to FPLINE pulse trailing edge
note 2
t2
FPFRAME hold from FPLINE pulse trailing edge
14 Ts (note 1)
t3
FPLINE pulse width
9Ts
t4
FPLINE period
note 3
t5
MOD transition to FPLINE pulse trailing edge
1 note 4 Ts
t6
FPSHIFT falling edge to FPLINE pulse leading edge
note 5
t7
FPLINE pulse trailing edge to FPSHIFT falling edge
t10 + t11 Ts
t8
FPSHIFT period
8Ts
t9
FPSHIFT falling edge to FPLINE pulse trailing edge
note 6
t10
FPLINE pulse trailing edge to FPSHIFT rising edge
20 Ts
t11
FPSHIFT pulse width high
4Ts
t12
FPSHIFT pulse width low
4Ts
t13
UD[3:0], LD[3:0] setup to FPSHIFT falling edge
4Ts
t14
UD[3:0], LD[3:0] hold to FPSHIFT falling edge
4Ts
t13 t14
FPFRAME
FPLINE
MOD
Sync Timing
FPLINE
FPSHIFT
UD[3:0]
LD[3:0]
Data Timing
t5
t1
t2
t4
t3
t10
t7 t8
t12t11
12
t9
t6