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Hardware Functional Specification S1D13505
Issue Date: 01/02/02 X23A-A-001-14
1. If the S1D13505 host interface is disabled, the timing for DTACK# driven high is relative to
the falling edge of CS#, AS# or
the first positive edge of CLK after A[20:1], M/R# becomes
valid,
whichever one is later.
2. If the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the fall-
ing edge of UDS#, LDS# or
the first positive edge of CLK after A[20:1], M/R# becomes valid,
whichever one is later.
Table 7-3: MC68000 Timing
3.0V 5.0V
Symbol Parameter Min Max Min Max Units
t1
Clock period
20 20 ns
t2
Clock pulse width high
66ns
t3
Clock pulse width low
66ns
t4
A[20:1], M/R# setup to first CLK where CS# = 0 AS# = 0, and
either UDS#=0 or LDS# = 0
10 10 ns
t5
A[20:1], M/R# hold from AS#
00ns
t6
CS# hold from AS#
00ns
t7
R/W# setup to before to either UDS#=0 or LDS# = 0
10 10 ns
t8
R/W# hold from AS#
00ns
t9
1
AS# = 0 and CS# = 0 to DTACK# driven high
00ns
t10
AS# high to DTACK# high
318312ns
t11
First BCLK where AS# = 1 to DTACK# high impedance
25 10 ns
t12
D[15:0] valid to third CLK where CS# = 0 AS# = 0, and either
UDS#=0 or LDS# = 0 (write cycle)
10 10 ns
t13
D[15:0] hold from falling edge of DTACK# (write cycle)
00ns
t14
2
Falling edge of UDS#=0 or LDS#=0 to D[15:0] driven (read
cycle)
00ns
t15
D[15:0] valid to DTACK# falling edge (read cycle)
00ns
t16
UDS# and LDS# high to D[15:0] invalid/high impedance (read
cycle)
5 25 2.5 10 ns
t17
AS# high setup to CLK
22ns