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Page 17
Vancouver Design Center
Hardware Functional Specification S1D13505
Issue Date: 01/02/02 X23A-A-001-14
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Figure 3-5: Typical System Diagram (Generic Bus)
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Figure 3-6: Typical System Diagram (NEC VR41xx (MIPS) Bus)
S1D13505F00A
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLKI
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0]
4/8/16-bit
LCD
Display
Generic
BUS
RESET#
D[15:0]
RD#
WAIT#
A[20:0]
BCLK
RD/WR#
AB[20:0]
DB[15:0]
WE1#
RD#
M/R#
CS#
BUSCLK
WAIT#
RESET#
A[27:21]
CSn#
WE1#
LCDPWR
WE#
A[11:0]
D[15:0]
RAS#
1Mx16
LCAS#
UCAS#
MA[11:0]
MD[15:0]
WE#
RAS#
LCAS#
UCAS#
FPM/EDO-DRAM
Decoder
WE0#
WE0#
Power
Management
SUSPEND#
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
IREF
IREF
S1D13505F00A
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLKI
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0]
4/8/16-bit
LCD
Display
MIPS
BUS
RESET
D[15:0]
MEMR#
RDY
A[20:0]
BCLK
RD/WR#
AB[20:0]
DB[15:0]
WE1#
RD#
M/R#
CS#
BUSCLK
WAIT#
RESET#
A[25:21]
CSn#
SBHE#
LCDPWR
WE#
A[11:0]
D[15:0]
RAS#
1Mx16
LCAS#
UCAS#
MA[11:0]
MD[15:0]
WE#
RAS#
LCAS#
UCAS#
FPM/EDO-DRAM
Decoder
WE0#
MEMW#
Power
Management
SUSPEND#
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
IREF
IREF
VDD