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Epson Research and Development
Page 19
Vancouver Design Center
Hardware Functional Specification S1D13505
Issue Date: 01/02/02 X23A-A-001-14
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Figure 3-9: Typical System Diagram (Power PC Bus)
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Figure 3-10: Typical System Diagram (PC Card (PCMCIA) Bus)
S1D13505F00A
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLKI
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0]
4/8/16-bit
LCD
Display
PowerPC
BUS
RESET#
TSIZ1
D[0:15]
TS#
RD/WR#
TSIZ0
TA #
A[11:31]
CLKOUT
WE0#
RD/WR#
AB[20:0]
DB[15:0]
WE1#
BS#
RD#
M/R#
CS#
BUSCLK
WAIT#
RESET#
A[0:10]
Decoder
Decoder
BI#
LCDPWR
WE#
A[8:0]
D[15:0]
RAS#
256Kx16
LCAS#
UCAS#
MA[8:0]
MD[15:0]
WE#
RAS#
LCAS#
UCAS#
FPM/EDO-DRAM
Power
Management
SUSPEND#
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
IREF
IREF
S1D13505F00A
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLKI
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0]
4/8/16-bit
LCD
Display
PC Card
BUS
RESET
D[15:0]
-OE
-WAIT
A[20:0]
BCLK
RD/WR#
AB[20:0]
DB[15:0]
WE1#
RD#
M/R#
CS#
BUSCLK
WAIT#
RESET#
A[25:21]
-CE2
LCDPWR
WE#
A[11:0]
D[15:0]
RAS#
1Mx16
LCAS#
UCAS#
MA[11:0]
MD[15:0]
WE#
RAS#
LCAS#
UCAS#
FPM/EDO-DRAM
WE0#
-WE
Power
Management
SUSPEND#
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
IREF
IREF
Decoder
Decoder
-CE1