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Page 15
Vancouver Design Center
Hardware Functional Specification S1D13505
Issue Date: 01/02/02 X23A-A-001-14
3 Typical System Implementation Diagrams
Figure 3-1: Typical System Diagram (SH-4 Bus)
.
Figure 3-2: Typical System Diagram (SH-3 Bus)
S1D13505F00A
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLKI
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0]
4/8/16-bit
LCD
Display
SH-4
BUS
RESET#
WE0#
D[15:0]
BS#
RD/WR#
RD#
RDY#
A[20:0]
CKIO
WE0#
RD/WR#
AB[20:0]
DB[15:0]
WE1#
BS#
RD#
M/R#
CS#
BUSCLK
WAIT#
RESET#
A[21]
CSn#
WE1#
LCDPWR
LCAS#
UCAS#
MA[8:0]
MD[15:0]
WE#
RAS#
Power
Management
SUSPEND#
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
IREF
IREF
WE#
A[8:0]
D[15:0]
RAS#
256Kx16
LCAS#
UCAS#
FPM/EDO-DRAM
S1D13505F00A
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLKI
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0]
4/8/16-bit
LCD
Display
SH-3
BUS
RESET#
WE0#
D[15:0]
BS#
RD/WR#
RD#
WAIT#
A[20:0]
CKIO
WE0#
RD/WR#
AB[20:0]
DB[15:0]
WE1#
BS#
RD#
M/R#
CS#
BUSCLK
WAIT#
RESET#
A[21]
CSn#
WE1#
LCDPWR
LCAS#
UCAS#
MA[8:0]
MD[15:0]
WE#
RAS#
Power
Management
SUSPEND#
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
IREF
IREF
WE#
A[8:0]
D[15:0]
RAS#
256Kx16
LCAS#
UCAS#
FPM/EDO-DRAM