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Epson Research and Development
Vancouver Design Center
S1D13505 Hardware Functional Specification
X23A-A-001-14 Issue Date: 01/02/02
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Figure 3-3: Typical System Diagram (MC68K Bus 1, 16-Bit 68000)
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Figure 3-4: Typical System Diagram (MC68K Bus 2, 32-Bit 68030)
S1D13505F00A
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLKI
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0]
4/8/16-bit
LCD
Display
MC68000
BUS
RESET#
LDS#
D[15:0]
AS#
R/W#
DTACK#
A[20:1]
BCLK
AB0#
RD/WR#
AB[20:1]
DB[15:0]
WE1#
BS#
M/R#
CS#
BUSCLK
WAIT#
RESET#
A[23:21]
FC0, FC1
Decoder
Decoder
UDS#
LCDPWR
LCAS#
UCAS#
MA[8:0]
MD[15:0]
WE#
RAS#
Power
Management
SUSPEND#
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
IREF
IREF
WE#
A[8:0]
D[15:0]
RAS#
256Kx16
LCAS#
UCAS#
FPM/EDO-DRAM
S1D13505F00A
FPFRAME
FPSHIFT
FPLINE
DRDY
FPDAT[15:8]
FPDAT[7:0]
CLKI
Oscillator
FPFRAME
FPSHIFT
FPLINE
MOD
UD[7:0]
LD[7:0]
4/8/16-bit
LCD
Display
MC68030
BUS
RESET#
SIZ0
D[31:16]
AS#
R/W#
SIZ1
DSACK1#
A[20:0]
BCLK
WE0#
RD/WR#
AB[20:0]
DB[15:0]
WE1#
BS#
RD#
M/R#
CS#
BUSCLK
WAIT#
RESET#
A[31:21]
FC0, FC1
Decoder
Decoder
DS#
LCDPWR
WE#
A[8:0]
D[15:0]
RAS#
256Kx16
LCAS#
UCAS#
MA[8:0]
MD[15:0]
WE#
RAS#
LCAS#
UCAS#
FPM/EDO-DRAM
Power
Management
SUSPEND#
RED,GREEN,BLUE
HRTC
VRTC
CRT
Display
IREF
IREF