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Epson Research and Development
Page 107
Vancouver Design Center
Programming Notes and Examples S1D13505
Issue Date: 01/02/05 X23A-G-003-07
Appendix A Supported Panel Values
A.1 Supported Panel Values
The following tables show related register data for different panels. All the examples are
based on 8 bpp and 2M bytes of 50 ns EDO-DRAM.
Note
The following settings may not reflect the ideal settings for your system configuration.
Power, speed, and cost requirements may dictate different starting parameters for your
system (e.g. 320x240@78Hz using 12MHz clock).
Table 12-1: Passive Single Panel @ 320x240 with
40MHz Pixel Clock
Register
Mono 4-Bit
320X240@60Hz
Mono 4-Bit
EL
320X240@60Hz
Color 8-Bit
320X240@60Hz
Color 8-Bit
Format 2
320X240@60Hz
Notes
REG[02h] 0000 0000 1000 0000 0001 0100 0001 1100 set panel type
REG[03h] 0000 0000 0000 0000 0000 0000 0000 0000 set MOD rate
REG[04h] 0010 0111 0010 0111 0010 0111 0010 0111 set horizontal display width
REG[05h] 0001 0111 0001 0111 0001 0111 0001 0111 set horizontal non-display period
REG[08h] 1110 1111 1110 1111 1110 1111 1110 1111 set vertical display height bits 7-0
REG[09h] 0000 0000 0000 0000 0000 0000 0000 0000 set vertical display height bits 9-8
REG[0Ah] 0011 1110 0011 1110 0011 1110 0011 1110 set vertical non-display period
REG[0Dh] 0000 1101 0000 1101 0000 1101 0000 1101 set 8 bpp and LCD enable
REG[19h] 0000 0011 0000 0011 0000 0011 0000 0011 set MCLK and PCLK divide
REG[1Bh] 0000 0001 0000 0001 0000 0001 0000 0001 disable half frame buffer
REG[24h] 0000 0000 0000 0000 0000 0000 0000 0000 set Look-Up Table address to 0
REG[26h] load LUT load LUT load LUT load LUT load Look-Up Table
Table 12-2: Passive Single Panel @ 640x480 with
40MHz Pixel Clock
Register
Mono 8-Bit
640X480@60Hz
Color 8-Bit
640X480@60Hz
Color 16-Bit
640X480@60Hz
Notes
REG[02h] 0001 0000 0001 0100 0010 0100 set panel type
REG[03h] 0000 0000 0000 0000 0000 0000 set MOD rate
REG[04h] 0100 1111 0100 1111 0100 1111 set horizontal display width
REG[05h] 0000 0011 0000 0011 0000 0011 set horizontal non-display period
REG[08h] 1101 1111 1101 1111 1101 1111 set vertical display height bits 7-0
REG[09h] 0000 0001 0000 0001 0000 0001 set vertical display height bits 9-8
REG[0Ah] 0000 0010 0000 0010 0000 0010 set vertical non-display period
REG[0Dh] 0000 1101 0000 1101 0000 1101 set 8 bpp and LCD enable
REG[19h] 0000 0001 0000 0001 0000 0001 set MCLK and PCLK divide
REG[1Bh] 0000 0001 0000 0001 0000 0001 disable half frame buffer
REG[24h] 0000 0000 0000 0000 0000 0000 set Look-Up Table address to 0
REG[26h] load LUT load LUT load LUT load Look-Up Table