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Epson Research and Development
Page 11
Vancouver Design Center
13505CFG Configuration Program S1D13505
Issue Date: 01/03/29 X23A-B-001-04
WE# Control Selects the WE# control used for the DRAM. DRAM
uses one of two methods of control when writing to
memory. These methods are referred to as 2-CAS# and
2-WE#.
The S5U13505 evaluation boards use DRAM requiring
the 2-CAS# method.
Refresh Time This value represents the number of ms required to
refresh 256 rows of DRAM.
Memory Performance These settings optimize the memory timings for best
performance. The default values change based on the
memory configuration (access time, memory type, etc.).
For further information on configuring these settings,
refer to the S1D13505 Hardware Functional Specifi-
cation, document number X23A-A-001-xx and the
DRAM manufacturer’s specification.
Suspend Mode Refresh Selects the DRAM refresh method used during power
save mode.
The S5U13505 evaluation boards use DRAM requiring
Self Refresh. For all other implementations, refer to the
manufacturer’s specification for DRAM refresh
requirements.
CAS before RAS Select this setting for DRAM that requires timing where
the CAS signal occurs before the RAS signal for low
power memory refresh.
Self refresh Select this setting for DRAM that requires no signal
from the S1D13505 to maintain memory refresh.
No refresh This selection does not refresh the memory during
power save mode. If this option is selected, the memory
contents are lost during power save.
Installed Memory Selects the amount of DRAM available for the display
buffer.
The S1D13505 evaluation boards have 2M bytes of
DRAM installed.