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Vancouver Design Center
Interfacing to the Toshiba MIPS TX3912 Processor S1D13505
Issue Date: 01/02/05 X23A-G-010-04
3 S1D13505 Host Bus Interface
The S1D13505 implements a 16-bit host bus interface specifically for interfacing to the
TX3912 microprocessor.
The TX3912 host bus interface is selected by the S1D13505 on the rising edge of RESET#.
After releasing reset, the bus interface signals assume their selected configuration. For
details on S1D13505 configuration, see Section 4.2, “S1D13505 Configuration” on page
12.
Note
At reset, the Host Interface Disable bit in the Miscellaneous Disable Register
(REG[1Bh] bit 7) is set to 1. This means that only REG[1Ah] (read-only) and
REG[1Bh] are accessible until a write to REG[1Bh] sets bit 7 to 0 making all regis-
ters accessible. When debugging a new hardware design, this can sometimes give the
appearance that the interface is not working, so it is important to remember to clear this
bit before proceeding with debugging.
3.1 TX3912 Host Bus Interface Pin Mapping
The following table shows the function of each host bus interface signal.
Table 3-1: TX3912 Host Bus Interface Pin Mapping
S1D13505
Pin Names
Toshiba TX3912
AB20 ALE
AB19 CARDREG*
AB18 CARDIORD*
AB17 CARDIOWR*
AB[16:13] V
DD
AB[12:0] A[12:0]
DB[15:8] D[23:16]
DB[7:0] D[31:24]
WE1# CARDxCSH*
M/R# V
DD
CS# V
DD
BUSCLK DCLKOUT
BS# V
DD
RD/WR# CARDxCSL*
RD# RD*
WE0# WE*
WAIT# CARDxWAIT*
RESET# PON*