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Epson Research and Development
Page 11
Vancouver Design Center
Interfacing to the PC Card Bus S1D13505
Issue Date: 01/02/05 X23A-G-005-06
3 S1D13505 Host Bus Interface
The S1D13505 implements a 16-bit PC Card (PCMCIA) host bus interface which is used
to interface to the PC Card bus.
The PC Card host bus interface is selected by the S1D13505 on the rising edge of RESET#.
After releasing reset the bus interface signals assume their selected configuration. For
details on S1D13505 configuration, see Section 4.2, “S1D13505 Hardware Configuration”
on page 15.
Note
At reset, the Host Interface Disable bit in the Miscellaneous Disable Register
(REG[1Bh] bit 7) is set to 1. This means that only REG[1Ah] (read-only) and
REG[1Bh] are accessible until a write to REG[1Bh] sets bit 7 to 0 making all regis-
ters accessible. When debugging a new hardware design, this can sometimes give the
appearance that the interface is not working, so it is important to remember to clear this
bit before proceeding with debugging.
3.1 PC Card Host Bus Interface Pin Mapping
The following table shows the functions of each host bus interface signal.
Note
1
The bus signal A0 is not used by the S1D13505 internally.
2
Although a clock is not directly supplied by the PC Card interface, one is required by
the S1D13505 PC Card host bus interface. For an example of how this can be accom-
plished see the discussion on BUSCLK in Section 3.2, “PC Card Host Bus Interface
Signals” on page 12.
Table 3-1: PC Card Host Bus Interface Pin Mapping
S1D13505 Pin Name PC Card (PCMCIA)
AB[20:0] A[20:0]
1
DB[15:0] D[15:0]
WE1# -CE2
M/R# External Decode
CS# External Decode
BUSCLK n/a
2
BS# V
DD
RD/WR# -CE1
RD# -OE
WE0# -WE
WAIT# -WAIT
RESET# Inverted RESET