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Epson Research and Development
Page 15
Vancouver Design Center
Interfacing to the PC Card Bus S1D13505
Issue Date: 01/02/05 X23A-G-005-06
4.2 S1D13505 Hardware Configuration
The S1D13505 latches MD15 through MD0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13505 Hardware Functional Specification, document number X23A-A-001-xx.
The table below shows only those configuration settings important to the PC Card host bus
interface.
4.3 Performance
The S1D13505 PC Card Interface specification supports a BCLK up to 50MHz, and
therefore can provide a high performance display solution.
Table 4-1: Summary of Power-On/Reset Options
S1D13505
Pin Name
value on this pin at rising edge of RESET# is used to configure:
(1/0)
10
MD0 8-bit host bus interface
16-bit host bus interface
MD[3:1] 111 = PC Card host bus interface selected
MD4 Little Endian Big Endian
MD5 WAIT# is active high (1 = insert wait state)
WAIT# is active low (0 = insert wait state)
MD11 Alternate Host Bus Interface Selected Primary Host Bus Interface Selected
MD12 BUSCLK input divided by two BUSCLK input not divided by two
= configuration for PC Card host bus interface