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Epson Research and Development
Vancouver Design Center
S1D13505 Hardware Functional Specification
X23A-A-001-14 Issue Date: 01/02/02
7.3.3 EDO-DRAM Self-Refresh Timing
Figure 7-17: EDO-DRAM Self-Refresh Timing
Table 7-17: EDO-DRAM Self-Refresh Timing
Symbol Parameter Min Max Units
t1
Internal memory clock period
25 ns
t2
RAS# precharge time (REG[22h] bits 3-2 = 00) 2 t1 - 3 ns
RAS# precharge time (REG[22h] bits 3-2 = 01) 1.45t1 - 3 ns
RAS# precharge time (REG[22h] bits 3-2 = 10) 1 t1 - 3 ns
t3
RAS# to CAS# precharge time (REG[22h] bits 3-2 = 00) 1.45t1 - 3 ns
RAS# to CAS# precharge time (REG[22h] bits 3-2 = 01 or 10) 0.45t1 - 3 ns
t4
CAS# setup time (REG[22h] bits 3-2 = 00 or 10)
0.45t1 - 3 ns
CAS# setup time (REG[22h] bits 3-2 = 01)
1 t1 - 3 ns
t5
CAS# precharge time (REG[22h] bits 3-2 = 00) 2 t1 - 3 ns
CAS# precharge time (REG[22h] bits 3-2 = 01 or 10) 1 t1 - 3 ns
RAS#
CAS#
t5
t3 t4
t2
Memory
Clock
Stopped for
suspend mode
Restarted for
active mode
t1