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Epson Research and Development
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S1D13505 Hardware Functional Specification
X23A-A-001-14 Issue Date: 01/02/02
REG[08h] bits 7-0 Vertical Display Height Bits [9:0]
REG[09h] bits 1-0 These bits specify the vertical display height.
Vertical display height (lines) = Vertical Display Height Bits [9:0] + 1
• For CRT, TFT/D-TFD, and single passive LCD panel this register is programmed to:
(vertical resolution of the display) - 1, e.g. EFh for a 240-line display.
• For dual-panel passive LCD not in simultaneous display mode, this register is programmed to:
((vertical resolution of the display)/2) - 1, e.g. EFh for a 480-line display.
• For all simultaneous display modes, this register is programmed to:
(vertical resolution of the CRT) - 1, e.g. 1DFh for a 480-line CRT.
bit 7 Vertical Non-Display Period Status
This is a read-only status bit.
When this bit = 1, a vertical non-display period is indicated.
When this bit = 0, a vertical display period is indicated.
bits 5-0 Vertical Non-Display Period Bits [5:0]
These bits specify the vertical non-display period.
Vertical non-display period (lines) = Vertical Non-Display Period Bits [5:0] + 1
Note
This register must be programmed such that
REG[0Ah]
≥
1 and (REG[0Ah] bits [5:0] + 1)
≥
(REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1)
Vertical Display Height Register 0
REG[08h] RW
Vertical
Display
Height Bit 7
Vertical
Display
Height Bit 6
Vertical
Display
Height Bit 5
Vertical
Display
Height Bit 4
Vertical
Display
Height Bit 3
Vertical
Display
Height Bit 2
Vertical
Display
Height Bit 1
Vertical
Display
Height Bit 0
Vertical Display Height Register 1
REG[09h] RW
n/a n/a n/a n/a n/a n/a
Vertical
Display
Height Bit 9
Vertical
Display
Height Bit 8
Vertical Non-Display Period Register
REG[0Ah] RW
Vertical Non-
Display
Period Status
(RO)
n/a
Vertical Non-
Display
Period Bit 5
Vertical Non-
Display
Period Bit 4
Vertical Non-
Display
Period Bit 3
Vertical Non-
Display
Period Bit 2
Vertical Non-
Display
Period Bit 1
Vertical Non-
Display
Period Bit 0