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Epson Research and Development
Vancouver Design Center
S1D13505 Programming Notes and Examples
X23A-G-003-07 Issue Date: 01/02/05
Step two involves setting the screen 1 start address registers. Set to 1024 - width for 16 bpp
modes and to (1024 - width) / 2 for 8 bpp modes.
Finally set the memory address offset registers to 1024 pixels. In 16 bpp mode load
registers [17h:16h] with 1024 and in 8 bpp mode load the registers with 512.
8.4 Limitations
The following limitations apply to SwivelView:
• Only 8/15/16 bpp modes are supported - 1/2/4 bpp modes are not supported.
• Hardware Cursor and Ink Layer images are not rotated - software rotation must be used.
SwivelView must be turned off when the programmer is accessing the Hardware Cursor
or the Ink Layer.
• Split screen images appear side-by-side, i.e. when SwivelView is enabled the screen is
split vertically.
• Pixel panning works vertically.
REG[0Dh] Display Mode Register
SwivelView
Enable
Simultaneous
Display
Option Select
Bit 1
Simultaneous
Display
Option Select
Bit 0
Bit-Per-Pixel
Select Bit 2
Bit-Per-Pixel
Select Bit 1
Bit-Per-Pixel
Select Bit 0
CRT Enable LCD Enable
REG[10h] Screen 1 Display Start Address Register 0
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
REG[11h] Screen 1 Display Start Address Register 1
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
REG[12h] Screen 1 Display Start Address Register 2
n/a n/a n/a n/a Bit 19 Bit 18 Bit 17 Bit 16
REG[16h] Memory Address Offset Register 0
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
REG[17h] Memory Address Offset Register 1
n/a n/a n/a n/a n/a Bit 10 Bit 9 Bit 8