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Epson Research and Development
Vancouver Design Center
S1D13505 Hardware Functional Specification
X23A-A-001-14 Issue Date: 01/02/02
bits 6-0 Horizontal Display Width Bits [6:0]
These bits specify the LCD panel and/or the CRT horizontal display width as follows.
Contents of this Register = (Horizontal Display Width
÷
8) - 1
For passive LCD panels the Horizontal Display Width must be divisible by 16, and for TFT LCD
panels/CRTs the Horizontal Display Width must be divisible by 8. The maximum horizontal dis-
play width is 1024 pixels.
Note
This register must be programmed such that REG[04h]
≥
3 (32 pixels)
Note
When setting a horizontal resolution greater than 767 pixels, with a color depth of 15/16 bpp, the
Memory Offset Registers (REG[16h], REG[17h]) must be set to a virtual horizontal pixel
resolution of 1024.
bits 4-0 Horizontal Non-Display Period Bits [4:0]
These bits specify the horizontal non-display period.
Horizontal non-display period (pixels) = (Horizontal Non-Display Period Bits [4:0] + 1)
×
8
The recommended minimum value which should be programmed into this register is 3 (32 pixels).
The maximum value which can be programmed into this register is 1Fh, which gives a horizontal
non-display period of 256 pixels.
Note
This register must be programmed such that
REG[05h]
≥
3 and (REG[05h] + 1)
≥
(REG[06h] + 1) + (REG[07h] bits [3:0] +1)
Horizontal Display Width Register
REG[04h] RW
n/a
Horizontal
Display Width
Bit 6
Horizontal
Display Width
Bit 5
Horizontal
Display Width
Bit 4
Horizontal
Display Width
Bit 3
Horizontal
Display Width
Bit 2
Horizontal
Display Width
Bit 1
Horizontal
Display Width
Bit 0
Horizontal Non-Display Period Register
REG[05h] RW
n/a n/a n/a
Horizontal
Non-Display
Period Bit 4
Horizontal
Non-Display
Period Bit 3
Horizontal
Non-Display
Period Bit 2
Horizontal
Non-Display
Period Bit 1
Horizontal
Non-Display
Period Bit 0