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Epson Research and Development
Page 51
Vancouver Design Center
Programming Notes and Examples S1D13505
Issue Date: 01/02/05 X23A-G-003-07
9 CRT Considerations
9.1 Introduction
The S1D13505 is capable of driving either an LCD panel, or a CRT display, or both simul-
taneously.
As display devices, panels tend to be lax in their horizontal and vertical timing require-
ments. CRT displays often cannot vary by more than a very small percentage in their timing
requirements before the image is degraded.
Central to the following sections are VESA timings. Rather than fill this section of the
guide with pages full of register values it is recommended that the program
13505CFG.EXE be used to generate a header file with the appropriate values. For more
information on VESA timings contact the Video Electronics Standards association on the
world-wide web at www.vesa.org.
9.1.1 CRT Only
All CRT output should meet VESA timing specifications. The VESA specification details
all the parameters of the display and non-display times as well as the input clock required
to meet the times. Given a proper VESA input clock the configuration program
13505CFG.EXE will generate correct VESA timings for 640x480 and for 800x600 modes.
9.1.2 Simultaneous Display
As mentioned in the previous section, CRT timings should always comply to the VESA
specification. This requirement implies that during simultaneous operation the timing must
still be VESA compliant. For most panels, being run at CRT frequencies is not a problem.
One side effect of running with these usually slower timings will be a flicker on the panel.
One limitation of simultaneous display is that should a dual panel be the second display
device the half frame buffer must be disabled for correct operation.