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Epson Research and Development
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S1D13505 Hardware Functional Specification
X23A-A-001-14 Issue Date: 01/02/02
5.4 Multiple Function Pin Mapping
Note
1
The bus signal A0 is not used by the S1D13505 internally.
Table 5-6: CPU Interface Pin Mapping
S1D1350
5
Pin
Names
SH-3 SH-4
MC68K
Bus 1
MC68K
Bus 2
Generic MIPS/ISA
Philips
PR31500
/PR31700
Toshiba
TX3912
PowerPC
PC Card
(PCMCIA)
AB20 A20 A20 A20 A20 A20 LatchA20 ALE ALE A11 A20
AB19 A19 A19 A19 A19 A19 SA19 /CARDREG CARDREG* A12 A19
AB18 A18 A18 A18 A18 A18 SA18 /CARDIORD CARDIORD* A13 A18
AB17 A17 A17 A17 A17 A17 SA17 /CARDIOWR CARDIOWR* A14 A17
AB[16:13] A[16:13] A[16:13] A[16:13] A[16:13] A[16:13] SA[16:13] V
DD
V
DD
A[15:18] A[16:13]
AB[12:1] A[12:1] A[12:1] A[12:1] A[12:1] A[12:1] SA[12:1] A[12:1] A[12:1] A[19:30] A[12:1]
AB0 A0
1
A0 LDS# A0 A0
1
SA0 A0
1
A0
1
A31 A0
1
DB[15:8] D[15:8] D[15:8] D[15:8] D[31:24] D[15:8] SD[15:8] D[31:24] D[31:24] D[0:7] D[15:8]
DB[7:0] D[7:0] D[7:0] D[7:0] D[23:16] D[7:0] SD[7:0] D[23:16] D[23:16] D[8:15 D[7:0]
WE1# WE1# WE1# UDS# DS# WE1# SBHE# /CARDxCSH CARDxCSH* BI# -CE2
M/R# External Decode V
DD
External Decode
CS# External Decode V
DD
External Decode
BUSCLK CKIO CKIO CLK CLK BCLK CLK DCLKOUT DCLKOUT CLKOUT CLKI
BS# BS# BS# AS# AS# V
DD
V
DD
V
DD
V
DD
TS# V
DD
RD/WR# RD/WR# RD/WR# R/W# R/W# RD1# V
DD
/CARDxCSL CARDxCSL* RD/WR# -CE1
RD# RD# RD# V
DD
SIZ1 RD0# MEMR# /RD RD* TSIZ0 -OE
WE0# WE0# WE0# V
DD
SIZ0 WE0# MEMW# /WE WE* TSIZ1 -WE
WAIT# WAIT# RDY DTACK# DSACK1# WAIT# IOCHRDY /CARDxWAIT CARDxWAIT* TA# -WAIT
RESET# RESET# RESET# RESET# RESET# RESET#
inverted
RESET
RESET# PON* RESET#
inverted
RESET