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Epson Research and Development
Page 65
Vancouver Design Center
Hardware Functional Specification S1D13505
Issue Date: 01/02/02 X23A-A-001-14
t12
Read Command Setup (REG[22h] bit 4 = 0 and bits
3-2 = 00)
4.45 t1 - 3 ns
Read Command Setup (REG[22h] bit 4 = 0 and bits
3-2 = 10)
3.45 t1 - 3 ns
Read Command Setup (REG[22h] bit 4 = 1 and bits
3-2 = 00)
3.45 t1 - 3 ns
Read Command Setup (REG[22h] bit 4 = 1 and bits
3-2 = 10)
2.45 t1 - 3 ns
Read Command Setup (REG[22h] bits 3-2 = 01) 3.45 t1 - 3 ns
t13
Read Command Hold (REG[22h] bit 4 = 0 and bits 3-
2 = 00)
3.45 t1 - 3 ns
Read Command Hold (REG[22h] bit 4 = 0 and bits 3-
2 = 10)
2.45 t1 - 3 ns
Read Command Hold (REG[22h] bit 4 = 1 and bits 3-
2 = 00)
2.45 t1 - 3 ns
Read Command Hold (REG[22h] bit 4 = 1 and bits 3-
2 = 10)
1.45 t1 - 3 ns
Read Command Hold (REG[22h] bits 3-2 = 01) 2.45 t1 - 3 ns
t14 Read Data Setup referenced from CAS# 5 ns
t15 Read Data Hold referenced from CAS# 3 ns
t16 Last Read Data Setup referenced from RAS# 5 ns
t17 Bus Turn Off from RAS# 3 t1- 5 ns
t18 Write Command Setup 0.45 t1- 3 ns
t19 Write Command Hold 0.45 t1 - 3 ns
t20 Write Data Setup 0.45 t1 - 3 ns
t21 Write Data Hold 0.45 t1 - 3 ns
t22 MD Tri-state 0.45 t1 0.45t1 + 21 ns
t23 CAS# to WE# active during Read-Write cycle 1 t1 - 3 ns
t24 Write Command Setup during Read-Write cycle 1.45 t1- 3 ns
t25
Last Read Data Setup referenced from WE# during
Read-Write cycle
10 ns
t26 Bus Tri-state from WE# during Read-Write cycle 0 t1- 5 ns
Table 7-15: EDO-DRAM Read/Write/Read-Write Timing
Symbol Parameter Min Max Units