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Epson Research and Development
Page 9
Vancouver Design Center
Programming Notes and Examples S1D13505
Issue Date: 01/02/05 X23A-G-003-07
List of Figures
Figure 3-1: Pixel Storage for 1 Bpp (2 Colors/Gray Shades) in One Byte of Display Buffer . . . . .16
Figure 3-2: Pixel Storage for 2 Bpp (4 Colors/Gray Shades) in One Byte of Display Buffer . . . . .17
Figure 3-3: Pixel Storage for 4 Bpp (16 Colors/Gray Shades) in One Byte of Display Buffer . . . .17
Figure 3-4: Pixel Storage for 8 Bpp (256 Colors/16 Gray Shades) in One Byte of Display Buffer . .18
Figure 3-5: Pixel Storage for 15 Bpp (32768 Colors/16 Gray Shades) in
Two Bytes of Display Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 3-6: Pixel Storage for 16 Bpp (65536 Colors/16 Gray Shades) in
Two Bytes of Display Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 5-1: Viewport Inside a Virtual Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 5-2: Memory Address Offset Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 5-3: Screen 1 Start Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 5-4: Pixel Panning Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 5-5: 320x240 Single Panel For Split Screen . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 5-6: Screen 1 Line Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 5-7: Screen 2 Display Start Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Figure 11-1: Components needed to build 13505 HAL application . . . . . . . . . . . . . . . . . . .78