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Epson Research and Development
Page 43
Vancouver Design Center
Hardware Functional Specification S1D13505
Issue Date: 01/02/02 X23A-A-001-14
Note
The SH-4 Wait State Control Register for the area in which the S1D13505 resides must be set to
a non-zero value. The SH-4 read-to-write cycle transition must be set to a non-zero value (with
reference to BUSCLK).
1. If the S1D13505 host interface is disabled, the timing for RDY# driven is relative to the falling
edge of CSn# or
the first positive edge of CKIO after A[20:0], M/R# becomes valid,
whichever one is later.
2. If the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the fall-
ing edge of RD# or
the first positive edge of CKIO after A[20:0], M/R# becomes valid,
whichever one is later.
Table 7-1: SH-4 Timing
3.0V
a
a
Two Software WAIT States Required
5.0V
b
b
One Software WAIT State Required
Symbol Parameter Min Max Min Max Units
t1
Clock period
15 15 ns
t2
Clock pulse width high
66ns
t3
Clock pulse width low
66ns
t4
A[20:0], M/R#, RD/WR# setup to CKIO
33ns
t5
A[20:0], M/R#, RD/WR# hold from CS#
00ns
t6
BS# setup
44ns
t7
BS# hold
11ns
t8
CSn# setup
44ns
t9
2
Falling edge RD# to D[15:0] driven
00ns
t10
Rising edge CSn# to RDY# tri-state
5252.510ns
t11
1
Falling edge CSn# to RDY# driven
015010ns
t12
CKIO to WAIT# delay
4 20 3.6 12 ns
t13
D[15:0] setup to 2
nd
CKIO after BS# (write cycle)
10 10 ns
t14
D[15:0] hold (write cycle)
00ns
t15
D[15:0] valid to RDY# falling edge (read cycle)
00ns
t16
Rising edge RD# to D[15:0] tri-state (read cycle)
5252.510ns