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S1D13505 S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual
X23A-G-004-05 Issue Date: 01/02/05
5 Host Bus Interface Pin Mapping
Table 5-1: CPU Interface Pin Mapping
S1D13505
Pin Names
SH-3 SH-4
MC68K
Bus 1
MC68K
Bus 2
Generic MIPS/ISA PowerPC PCMCIA
AB20 A20 A20 A20 A20 A20 LatchA20 A11 A20
AB[16:13] A[19:13] A[19:13] A[19:13] A[19:13] A[19:13] SA[19:13] A[12:18] A[19:13]
AB[12:1] A[12:1] A[12:1] A[12:1] A[12:1] A[12:1] SA[12:1] A[19:30] A[12:1]
AB0 A0 A0 LDS# A0 A0 SA0 A31 A0
DB[15:0] D[15:0] D[15:0] D[15:0] D[31:16] D[15:0] SD[15:0] D[0:15] D[15:0]
WE1# WE1# WE1# UDS# DS# WE1# SBHE# BI# -CE2
M/R# External Decode
CS# External Decode
BUSCLK CKIO CKIO CLK CLK BCLK CLK CLKOUT CLKI
BS# BS# BS# AS# AS# V
DD
V
DD
TS# V
DD
RD/WR# RD/WR# RD/WR# R/W# R/W# RD1# V
DD
RD/WR# -CE1
RD# RD# RD# V
DD
SIZ1 RD0# MEMR# TSIZ0 -OE
WE0# WE0# WE0# V
DD
SIZ0 WE0# MEMW# TSIZ1 -WE
WAIT# WAIT# RDY DTACK# DSACK1# WAIT# IOCHRDY TA# -WAIT
RESET# RESET# RESET# RESET# RESET# RESET#
inverted
RESET
RESET#
inverted
RESET