Filter
Top Products
Page 10
Epson Research and Development
Vancouver Design Center
S1D13505 Interfacing to the NEC VR4121™ Microprocessor
X23A-G-011-04 Issue Date: 01/02/05
3 S1D13505 Host Bus Interface
The S1D13505 directly supports multiple processors. The S1D13505 implements a 16-bit
MIPS/ISA Host Bus Interface which is most suitable for direct connection to the VR4121
microprocessor.
The MIPS/ISA host bus interface is selected by the S1D13505 on the rising edge of
RESET#. After releasing reset the bus interface signals assume their selected configuration.
For details on S1D13505 configuration, see Section 4.2, “S1D13505 Configuration” on
page 13.
Note
At reset, the Host Interface Disable bit in the Miscellaneous Disable Register
(REG[1Bh] bit 7) is set to 1. This means that only REG[1Ah] (read-only) and
REG[1Bh] are accessible until a write to REG[1Bh] sets bit 7 to 0 making all regis-
ters accessible. When debugging a new hardware design, this can sometimes give the
appearance that the interface is not working, so it is important to remember to clear this
bit before proceeding with debugging.
3.1 Host Bus Interface Pin Mapping
The following table shows the functions of each host bus interface signal.
Table 3-1: Host Bus Interface Pin Mapping
S1D13505 Pin Name NEC VR4121 Pin Name
AB20 ADD20
AB[19:0] ADD[19:0]
DB[15:0] DAT[15:0]
WE1# SHB#
M/R# ADD21
CS# LCDCS#
BUSCLK BUSCLK
BS# Connected to V
DD
RD/WR# Connected to V
DD
RD# RD#
WE0# WR#
WAIT# LCDRDY
RESET# connected to system reset