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Epson Research and Development
Page 13
Vancouver Design Center
Hardware Functional Specification S1D13505
Issue Date: 01/02/02 X23A-A-001-14
2.3 Display Support
• 4/8-bit monochrome passive LCD interface.
• 4/8/16-bit color passive LCD interface.
• Single-panel, single-drive displays.
• Dual-panel, dual-drive displays.
• Direct support for 9/12-bit TFT/D-TFD; 18-bit TFT/D-TFD is supported up to 64K color depth
(16-bit data).
• Embedded RAMDAC (DAC)with direct analog CRT drive.
• Simultaneous display of CRT and passive or TFT/D-TFD panels.
2.4 Display Modes
• 1/2/4/8/15/16 bit-per-pixel (bpp) support on LCD/CRT.
• Up to 16 shades of gray using FRM on monochrome passive LCD panels.
• Up to 4096 colors on passive LCD panels; three 256x4 Look-Up Tables (LUT) are used to map
1/2/4/8 bpp modes into these colors, 15/16 bpp modes are mapped directly using the 4 most
significant bits of the red, green and blue colors.
• Up to 64K colors on TFT/D-TFD LCD panels and CRT; three 256x4 Look-Up Tables are used to
map 1/2/4/8 bpp modes into 4096 colors, 15/16 bpp modes are mapped directly.
2.5 Display Features
• SwivelView™: direct hardware 90° rotation of display image for “portrait” mode display.
• Split Screen Display: allows two different images to be simultaneously viewed on the same
display.
• Virtual Display Support: displays images larger than the display size through the use of panning.
• Double Buffering/multi-pages: provides smooth animation and instantaneous screen update.
• Acceleration of screen updates by allocating full display memory bandwidth to CPU (see
REG[23h] bit 7).
• Hardware 64x64 pixel 2-bit cursor or full screen 2-bit ink layer.
• Simultaneous display of CRT and passive panel or TFT/D-TFD panel.
• Normal mode for cases where LCD and CRT screen sizes are identical.
• Line-doubling for simultaneous display of 240-line images on 240-line LCD and 480-line
CRT.
• Even-scan or interlace modes for simultaneous display of 480-line images on 240-line LCD
and 480-line CRT.
2.6 Clock Source
• Single clock input for both the pixel and memory clocks.
• Memory clock can be input clock or (input clock/2), providing flexibility to use CPU bus clock
as input.
• Pixel clock can be the memory clock, (memory clock/2), (memory clock/3) or (memory clock/4).