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Epson Research and Development
Page 21
Vancouver Design Center
Hardware Functional Specification S1D13505
Issue Date: 01/02/02 X23A-A-001-14
4.2.4 Memory Controller
The Memory Controller block arbitrates between CPU accesses and display refresh accesses as well
as generates the necessary signals to interface to one of the supported 16-bit memory devices (FPM-
DRAM or EDO-DRAM).
4.2.5 Display FIFO
The Display FIFO block fetches display data from the Memory Controller for display refresh.
4.2.6 Cursor FIFO
The Cursor FIFO block fetches Cursor/ink data from the Memory Controller for display refresh.
4.2.7 Look-Up Tables
The Look-Up Tables block contains three 256x4 Look-Up Tables (LUT), one for each primary
color. In monochrome mode, only the green LUT is selected and used. This block contains anti-
sparkle circuitry. The cursor/ink and display data are merged in this block.
4.2.8 CRTC
The CRTC generates the sync timing for the LCD and CRT, defining the vertical and horizontal
display periods.
4.2.9 LCD Interface
The LCD Interface block performs Frame Rate Modulation (FRM) for passive LCD panels and
generates the correct data format and timing control signals for various LCD and TFT/D-TFD
panels.
4.2.10 DAC
The DAC is the Digital to Analog converter for analog CRT support.
4.2.11 Power Save
The Power Save block contains the power save mode circuitry.
4.2.12 Clocks
The Clocks module is the source of all clocks in the chip.