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x Intel® PXA255 Processor Developer’s Manual
Contents
12.6.1 UDC Control Register (UDCCR).......................................................................12-22
12.6.2 UDC Control Function Register (UDCCFR)......................................................12-24
12.6.3 UDC Endpoint 0 Control/Status Register (UDCCS0) .......................................12-25
12.6.4 UDC Endpoint x Control/Status Register (UDCCS1/6/11)................................12-27
12.6.5 UDC Endpoint x Control/Status Register (UDCCS2/7/12)................................12-29
12.6.6 UDC Endpoint x Control/Status Register (UDCCS3/8/13)................................12-31
12.6.7 UDC Endpoint x Control/Status Register (UDCCS4/9/14)................................12-32
12.6.8 UDC Endpoint x Control/Status Register (UDCCS5/10/15)..............................12-34
12.6.9 UDC Interrupt Control Register 0 (UICR0) .......................................................12-36
12.6.10 UDC Interrupt Control Register 1 (UICR1) .......................................................12-38
12.6.11 UDC Status/Interrupt Register 0 (USIR0).........................................................12-39
12.6.12 UDC Status/Interrupt Register 1 (USIR1).........................................................12-41
12.6.13 UDC Frame Number High Register (UFNHR)..................................................12-42
12.6.14 UDC Frame Number Low Register (UFNLR) ...................................................12-44
12.6.15 UDC Byte Count Register x (UBCR2/4/7/9/12/14) ...........................................12-44
12.6.16 UDC Endpoint 0 Data Register (UDDR0).........................................................12-45
12.6.17 UDC Endpoint x Data Register (UDDR1/6/11) .................................................12-46
12.6.18 UDC Endpoint x Data Register (UDDR2/7/12) .................................................12-46
12.6.19 UDC Endpoint x Data Register (UDDR3/8/13) .................................................12-47
12.6.20 UDC Endpoint x Data Register (UDDR4/9/14) .................................................12-47
12.6.21 UDC Endpoint x Data Register (UDDR5/10/15) ...............................................12-48
12.7 USB Device Controller Register Summary....................................................................12-48
13 AC’97 Controller Unit..................................................................................................................13-1
13.1 Overview..........................................................................................................................13-1
13.2 Feature List......................................................................................................................13-1
13.3 Signal Description............................................................................................................13-2
13.3.1 Signal Configuration Steps .................................................................................13-2
13.3.2 Example AC-link .................................................................................................13-2
13.4 AC-link Digital Serial Interface Protocol...........................................................................13-3
13.4.1 AC-link Audio Output Frame (SDATA_OUT)......................................................13-4
13.4.2 AC-link Audio Input Frame (SDATA_IN).............................................................13-8
13.5 AC-link Low Power Mode ..............................................................................................13-12
13.5.1 Powering Down the AC-link..............................................................................13-12
13.5.2 Waking up the AC-link ......................................................................................13-13
13.6 ACUNIT Operation.........................................................................................................13-14
13.6.1 Initialization.......................................................................................................13-15
13.6.2 Trailing bytes ....................................................................................................13-17
13.6.3 Operational Flow for Accessing CODEC Registers..........................................13-17
13.7 Clocks and Sampling Frequencies................................................................................13-17
13.8 Functional Description...................................................................................................13-18
13.8.1 FIFOs................................................................................................................13-18
13.8.2 Interrupts...........................................................................................................13-19
13.8.3 Registers...........................................................................................................13-19
13.9 AC’97 Register Summary..............................................................................................13-35
14 Inter-Integrated-Circuit Sound (I2S) Controller...........................................................................14-1
14.1 Overview..........................................................................................................................14-1
14.2 Signal Descriptions..........................................................................................................14-2
14.3 Controller Operation ........................................................................................................14-3