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Intel® PXA255 Processor Developer’s Manual 14-15
Inter-Integrated-Circuit Sound (I2S) Controller
14.7 Interrupts
The following SASR0 status bits, if enabled, interrupt the processor:
• Receive FIFO Service DMA Request (RFS)
• Transmit FIFO Service DMA Request (TFS)
• Transmit Under-run (TUR)
• Receive Over-run (ROR).
Note: For further details, see Section 14.6.3.
14.8 I
2
S Controller Register Summary
All registers are word addressable (32 bits wide) and hence increment in units of 0x00004. All
I2SC registers are mapped in the address range of 0x4040_0000 through 0x4040_0080, as shown
in Table 14-12.
Figure 14-3. Transmit and Receive FIFO Accesses Through the SADR
TxEntry0
TxEntry1
TxEntry2
TxEntry3
TxEntry15
31
Right Left
16 15 0
RxEntry0
RxEntry1
RxEntry2
RxEntry3
RxEntry15
31
Right Left
16 15 0
SADR Register
31 0
Processor/DMA
TxFIFO
Written
Processor/DMA
RxFIFO
Read
PCM Transmit FIFO PCM Receive FIFO
Write
Read
Transmit Data Receive Data